The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication and resulting structures for fabricating a double gate planar two-dimensional material metal oxide semiconductor field effect transistors (MOSFET) with a small overlap capacitance between a back gate and a source/drain contact.
Semiconductor devices are typically formed using active regions of a wafer. In an integrated circuit (IC) having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by incorporating n-type or p-type impurities in the layer of semiconductor material. A conventional geometry for MOSFETs is known as a planar device geometry in which the various parts of the MOSFET device are laid down as planes or layers.
Traditional metal oxide semiconductor field effect transistor (MOSFET) fabrication techniques include process flows for constructing planar field effect transistors (FETs). A planar FET includes a substrate (also referred to as a silicon slab), a gate formed over the substrate, source and drain regions formed on opposite ends of the gate, and a channel region near the surface of the substrate under the gate. The channel region electrically connects the source region to the drain region while the gate controls the current in the channel. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).